Sequential pulse generator employing plurality of cascaded circuits coupled through shift gates and having individual output gates



Feb. 2, 1965 w. J. GESEK ETAL 3,168,700

SEQUENTIAL PULSE. GENERATOR EMPLOYING PLURALITY 0F CASCADED CIRCUITS COUPLED THROUGH SHIFT GATES AND HAVING INDIVIDUAL OUTPUT GATES Filed March 20, 1963 3 Sheets-Sheet 2 N INVENTORS III/1.04M J 6635K J-wzs Hie/1600M @MKU WM drramvzr 1965 w. J. GESEK ETAL 3,168,700

SEQUENTIAL PULSE GENERATOR EMPLOYING PLURALITY 0F CASCADED CIRCUITS COUPLED THROUGH SHIFT GATES AND HAVING INDIVIDUAL OUTPUT GATES United States Cherry Hill, N.J., assignors to Radio Corporation-of America, a corporation of-De'law'are' Filed Mar. 20,1963, Ser. No. 266,751 v I Claims} ((1328-62)- This invention relates'to a sequential pulse generator and has for its Object the provision of improved'meansfor generating a controllable number of sequential pulses on separate outputlines; 'These pul'ses'may-be used in a computer to control the sequential performance of elementary partsof machine instructions havinglvarying numbers of elementary parts.

' According to an example of the invention there are provided a plurality of cascaded preselection flip-flops coupled in cascade through shift gates and having in dividual output gates; There is also a last preselection'. flip-flop having an output gate. I An oscillation-controlled means is coupled to the-shift gates and output gates of the cascaded preselection flip-flops to cause the generation of'sequential output'clock pulses therefrom. Transfer gates are associated with the outputs of some of said cascaded preselection flip-flops to operate in response "to a pulse number control signal to cause the next following clock pulses to be generated from the lastpre'selection FIG.'1 is a chart of waveforms which will be referred,

to in describing the operation of the'invention in generating controllable numbers of output clock pulses;

FIGS. 2A and 2B show a clock pulse generator constructed according to the teachings of the invention; and

FIG. 3 is a key defining thelogic element symbols in and 2B in terms of associated.

the system of FIGS. 2A truth tables.

a Description Referring nowin greater detail to FIGS. 2A and 2B, the system shown is made up of conventional circuit elements represented by symbols which aredefined by associated truth tables in FIG. 3. The system of FIGS.

2A and 2B includes as many preselection flip-flops FF-L- FF-Z, FF-3, FF-4, FF-S, FF-6 and FF-L (L for last) as the maximum number of' clock pulses desired from a corresponding number of clock pulse output terminals CP-l, CP-Z, CP-3, CP-4, CP-S, CP.-6 and CP-L. .The number of output clock pulses generated at any particular time is three, five or seven depending on which one of the input pulse number signal level lines 3CP, SCP and 7CP is energized. v

The 1 outputs of preselection flip-flops-FF-l through FF-L are connected to inputs of corresponding output nor gates 11, 12, 13, 14, 15, 16*and IL. The 1 outputs of the preselection flip-flops FF-l, FF2, FF3, FF-4, FF-S and FF-L ,are also connected to inputs of corresponding shift nor gates 1, 2, 3, 4, 5 and L. The outputs of shift nor, gates 1,2, 3, 4 and 5 are connected in the manner of a shift register or counter, to set inputs of next following preselection flip-flops and to reset inputs of next'preceding preselection flip-flops. Each of preselection flip-flops FF-l through FF-6 together with their associated transfer and output gates constitute cascaded transfer nor circuits. .The last "preselection flip-flop FF-L together. with its shift gate L and output gate 1L constitutes a last circuit. The output of shift nor gate L is connected over bus 40 to the set input of preselection flip-flop FF-l and to the reset inputs of preselection .flip-flops FI -2,. FF-4andFF-6. V

The pulse number controlsignal input lines 3CP and SCP are connected respectively to inputs of shift ""nor gates 2 and 4. The input lines 3GP, S CP and 7CP are connected respectively through inverters to inputs of respective inverters to the outputs of respective output nor gates- 12, '14 and 16. Qutputs of -transfer nor. gates 22, 2 4 and 26 are gate 30 having an output connected through an inverter to an input'of a'fnor gate 31. The output terminal OSC-C of a 'source of oscillations is also connected-to an input of .nor gate 31. Theoutput of nor" gate31 is connected over a bus 42 to reset inputs ofpreselection flip-flops FF.-1, FF-3 and FF-S, and to a set input of preselection flip-flop FF-L.

. Bus 42 alsoextendsinto. FIG. 2Bi to the set input of last pulse synchronizing flipflop SFF-L. The output of output norgate 1L- ;in'FlG. '2A is connecteds through-an inverter and through a line 44 extending into gate 32. Anotherinput FIG. 2B to an'input of a nor of nor gate 32 receives oscillations from a terrninal OSC-C. The output of nor. gate 32 is connected; to the reset input of the synchronizingflip-flop SPF-Ll,

The nor gate 32, the synchronizingflip-fiop SFF L the .nor gates 33 and 34, andthe control flip-flop CFF-L; in FIG. 2B constitute an oscillation-controlled means or an alternator means 27 to control the gating out of the,-

last output clock pulse CP-L. The nor gates 35 and 36,=the synchronizing flip-flop SPF-16; the nor" gates 37 and 38, and the control flip-flop'CFF-16 constitute. an; oscillation-controlled means or. alternator means 28 to control the gating out of the other clock pulses CP-l through CP- 6.

The "1 output of synchronizing flip-flop SFF-L is connected to aninput of nor gate 33 which has its output connected to a reset input of control flip-flop CFF-L, and the 0 output of flip-flop SFF-L is connected to an input of nor gate 34 which has its output connected to the set input of flip-flop CFF-L.

The .fnor gates 35 and 36 have inputs connected to the OSC-C. terminal and have outputs connected tothe set and reset inputs, respectively, of synchronizing flip-- flop SPF-16. The l'output of flip-flop, SFF-16 is con-- nected to an input of -nor gate 37'which has its output connected to the reset inputof contol flip-flop (EFF-16. The 0. output of the flip-flop SPF-16 .is .connected'to an input of the"nor gate 38 which has its output con-' nected to a setinput of control flip-flop CFF-16. Output terminals OSC-B of a source of oscillations are connected toinputs of .nor gates 33, 34, 37 'and'38. A terminal OPERATE is connected toinputs of nor gates 33, 34,

37 and '38. The "0 output of s'ynchronizing-flip-flop SPF-L is also connected overa line 39 to inputs of nor gates 37Iand 38 to provide an interlocking connection between-alternator means 27 and 28 7 The 0 output of control flip-flop CFF-L is connected over bus 46 to inputs of shift nor gate L and output' nor gate 1L, and the 1 output is connected over bus Patented Feb., 2, 1965' I gates 22, 24 and 26. Other inputs of transfer no'r-- gates 22, 24 and26are connected through;

connected to inputs of an for? "and16.

: 'viding five output clock and'CP-L; e

- essence H 485th inputsof output nor? gates 12, 14 and 16. "The output of control flip-flop CPR-16 is connected over a bus 56 to inputs of shift and output .nor gates 1, 111, 3, 13, and 15, andthe"l. output is connected over bus 52 to inputs of shift and output nor'gates 2; 12, 4, 14

Operation 7 v V p j The operation of the systen i will now be described, with reference to FIGS. 1, 2A and 2B. Initially, a general re- .setisign al is applied to all of 'termi'nals GR to cause lastf control flip-flop CFFeL to be reset; to cause the-other l control flip-flop OFF-16 to be set;to cause cascaded preseleetion flip-flops FF-l through FF-o to be reset; and to cause the last preselection flip-flop FI L to be set. The

low output of the last preselection flipflop FF-L and the low signal on the 0 output bus 46 of control flipflop CFF- L enable gate L and causes'asignal over bus} 4 0 to set preselection flip-flop FF-l, and these signals also enable gate 1L and cause a signal over line 44 tending v t'o ienable gate 32.; On the next negative half-cycle of tam attacked b as at '4 silica has a-highli nput levelfro-rn lead-5GP. The inputs toi transfer' gate 24 en}; able the gate so that'a signal goesjoveiline 25,-"through or gate 30, and' an inverter to gate 31. 'When the' next negative half cycle of oscillation OSC-C ('FIG.vlc)- is present at time 69 at the input of gate 31',the output a of gate 31 acts over line 42] to presetfiip-flops'FF-l, "FF-V3 and FF-S and to Set the lastlflip-ifio p FF-Ll and it acts 1 over line 42 to set the synchronizing flip-flop SPF-L (FIG.

1)), The "0 output of flipfiop SFF -L goes.high so thatlit no longer enables gates 37 and 38 withithezresult that control fliPrflOP EFF-16 stops alternating, i.e.; 'remains set at the time 70'of the next negative half cycle of oscillation OSC-B. The fl output of flip-flop SFF-L enablesgate 33 for the next negative halfcycle of oscilla-l tions OSC-B atrtime 70. The outputof gate 33' resets control flip-flop CFF-L (FIG. -1g) so that its "1 output 7 goes rhigh and inhibits .outputjg'ate l4 and terminates; the CP-4 output pulse 68. The -"0 output of control flip-flop the oscillatioriOSC-C, gateBZ resets switch fiiprflop S FF- Land gate 35 setsswitch flip-flop SPF-16. The foregoing. states the'j conditions or all flip-flops following general reset. V I

sented'by the' waveforrnjofFIGfla.

' A start or operate signal applied to terrninal OPERATE enables-' gate' 34 (FIG; 2B 'so thatthe next negative half 'Vc'y'cle at time 60 of o scillationlQSC B (FIG. 1b) goes through ate 34' and {causes control Iflip' flo'p CFF-L (FIGilg) to beset, and the 'operatesignal enables gate 37 so that the negative half cycle*of oscillation ()SO-B OFF-46 enables output gate ll' providinga CP- l' (FIG. lh) clock output pulse 61,'1and enables shift gate 1 which acts over line 720, to; set flipflbpFF-Z; and a ctsfover linei 121to -reset flip-fiop-FF-L. w

cycle of oscillation OSC-B whichat time 63 sets control schenie can be applied CFE -L' goes 'through enabled gate Land overline 40 to 1 goes through enabled gate lL togprovidea last CP L foutputlclockpulsez 71. output 'clock-pulse 71 also following seriesofclock pulses. The generation of clock pulses then repeats in the manner' that has'been described.

The numberof'cloclg pulses generated in'each series of r At-the end'of the'negative half cycle of oscillation l QsC -B'and the beginning oflthe negative halfcycleofj oscillation OSC-C at time 62, gate 36 is enabled causing 7 "synchronizing flip-flop SPF-"16 (FIG, id) to bereset and V I its "0:o1itput enables gate '38 for the next negative half eesaw flip-flop CFF-LIG-then no wa er passes through 7 output gate 11 with the result that output clock pulse- CP- l'is terminated; TheJI output on lead 52. of con trol flip-flop OFF- 16 goes through output gate '12-'caus iug the CP Z clock pulse 64 to appear at output terminal 7 CP-;-2;(FIG. 1i); and it goes through'shift gateZto set flip-flop1FF-3 and. to reset flip-flop FF-l if shift gate 2} isc'enable'd by a low signal level" on the three-clock-pulse signal input lead 3GP. Lead 3GP would be high if. three output clock pulses CP-.1,- (DP-2 and- CP-L were desired." .1 It willlbe 'as'sumedthat-input lead 3GP is low r and that inputlead SCP is .high fol-the purpose of pro- {The next negative half cycle or oscillations OS C-jB at time 6,51resets'conuol flip-flop CFF-lfi (FIG. let) so' that "Them the next foll owing negative halfcycle of oscil-. lation 989 B at'tirue'6 7 causes control flip-flop CFF-6 1 '(FIG. 1e) to be set so that its 1 output goes through output gate 14 as a CP output clock pulser68 and goes pulslesCP-l; can, op-3', (JP-4 -its 0?? output goes through output gate 13 as a'CP-i V output clock pulse 66 (FIG. 11') and goes through shift lgoes'through an inverter and overa line 44; t o-enable gate 32for the neirt occurring negative:halfoycleofoscilla "tion OSC -C at time'72, at-which tithe synchronizing fiip flop S FE L is reset. The; 30 output offiipflQp SFF-EL enables gate 34 for the next negative halflcycle of oscil- 30 lation OSCeB at time7 which sets control flip-flop CFE- L so that its "0 outputfg'oes ihigh and terminates the last C Pl-L control pulse 71. Q: V i

V V The 0 output (flowgoi synchroniz ing flip-flop SPF- Lalso enables gate 37 so'thatfthenegatiyefhalf cycle of OS C-B at -tin1e.73 resets control flip-flop CFF- l oscillation 116.

r output enables output gate 11p to provic le the CF71 output clock pulse74 of the next clock pulses depends on the lfhigh input signal level applied'to ,ong ofthe pulse number determining input lines a j SQR' SCP and7CB; If thereis ajh igh, signal level on input line 3CP, fie,systerngenerates output pulses CP'1',"

CP-Z If there is a ?highlsignal level on input line 5C1, theis ystem generates output pulses'CP-LCPQ,

V (3P-3, CP-4 and CP-LI If the'r e is a high signal level on I input line 7GP, the system .gener atesloutput pulses CF- 1,]

CP2,"CP3, IP-4 CR-S, CP-fi and CP-L. The same to the generation or lly desired numbr'of" ea: Pulses. j What is claimed is: I 7

l lfMeansfor generatingacontrollable number se- I quentialclock'pulses, comprising c a a pluralityof cascaded circuits and a last circuitgeach a of said circuits having-an output lead, a a

- a, firstloscillatiomcontrelled means coupled to case I 'cadedlcircuits to cause successive V from said cascaded circuits, l 7' a second oscillation-controlled means coupled to said lastcircuit; and i 7' 1 clock pulse outputs transfer" gate means responsive'toloutputs of saidicascad'ed circuits and to a'pu'l'se numberidetermining "input signal to stop said first oscillation controlled, I

i means and activate said secondoscillation-controlled "L 111163.118; r e

2k Means for generating a controllable of sequentialclock pulses on separate output leads, comprising a plurality ofrcasca ded circuits and -a,last circuitpe-achg of said-circuits being'coupled to" a respective one of l saidvoutput leads, V 1 v 7 V i c a first oscillation-controlled nieansi coupled to said cascaded circuits to cause successive'cl'ockpulse outputs from said cascaded circuits, a

' a second oscillation-controlled means coupled to said last circuit,

at least one pulse member control signal input terminal,

and

at least one transfer gate means responsive to a signal on said control signal input terminal and a clock pulse output of one of said cascaded circuits and operative to stop said first oscillation-controlled means and activate said second oscillation-controlled means.

3. Means for generating a controllable number of sequential clock pulses on separate output leads, comprising a plurality of cascaded. circuits and a last circuit, each of said circuits being coupled to a respective one of said output leads,

a first oscillation-controlled means coupled to said cascaded circuits to cause successive clock pulse outputs from said cascaded circuits,

a second oscillation-controlled means interlocked with said second oscillation-controlled means and coupled to said last circuit,

a plurality of pulse member control signal input terminals, and

a plurality of transfer gate means each responsive to a signal on one of said input terminals and a clock pulse output of one of said cascaded circuits and operative to stop said first oscillation-controlled means and activate said second oscillation-controlled means.

4. Means for generating a controllable number of sequential clock pulses on separate output lines, comprising a plurality of preselection flip-flops,

shift gates coupling all but a last one of said flip-flops in cascade,

a plurality of output gates coupled between respective preselection flip-flops and respective output lines,

oscillation-controlled means coupled to said shift gates and output gates to providesuccessive output clock pulses, and

at least one transfer gate means responsive to a respective output clock pulse and a respective input signal to cause a following clock pulse from the last one of said preselection flip-flops.

5. Means for generating a controllable number of sequential clock pulses on separate output lines, comprising a plurality of preselection flip-flops,

shift gates coupling all but a last one of said flip-flops in cascade,

a plurality of output gates coupled between respective preselection flip-flops and respective output lines,

a first oscillation-controlled means coupled to said shift gates and output gates associated with all but the last of said flip-flops to provide successive output clock pulses,

a second oscillation-controlled means coupled to the output gate associated with the last flip-flop.

a pulse number input signal terminal, and

a transfer gate means responsive to a respective output clock pulse and a signal on said input signal terminal to stop said first oscillation-controlled means and activate said second oscillation-controlled means.

6. Means for generating a controllable number of sequential clock pulses on separate output lines, comprising a plurality of preselection flip-flops,

shift gates coupling all but a last one of said flip-flops in cascade,

a plurality of output gates coupled between respective preselection flip-flops and respective output lines,

a first oscillation-controlled means coupled to said shift gates and output gates associated with all but the last of said flip-flops to provide successive output clock pulses,

a plurality of pulse number determining input signal terminals, and

a plurality of transfer gate means each having an input coupled to a respective one of said terminals and an input coupled to one of said clock pulse output lines, said transfer gate means being operative to stop said first oscillation-controlled means and activate said second oscillation-controlled means. 7. Means for generating a controllable number of sequential clock pulses on separate output leads, comprising a plurality of cascaded circuits coupledin cascade through shift gates, and a last circuit,

output gates coupling outputs of respective circuits to said separate output leads,

a first oscillation-controlled means coupled to shift gates and output gates associated with said cascaded circuits .to provide sequential output clock pulses from said cascaded circuits,

a second oscillation-controlled means coupled to the output gate associated With said last circuit, and

at least one transfer gate responsive to a control input signal, to the gated output of an associated cascaded circuit and to said first oscillation-controlled means to stop the output of said first oscillation-controlled means and cause an output from said second oscillation-controlled means, whereby to determine the number of sequential output clock pulses from said cascaded circuits which precede an output clock pulse from said last circuit.

8. Means for generating a controllable number of sequential clock pulses on separate output leads, comprising a plurality of cascaded preselection flip-flops coupled in cascade through shift gates, and a last preselection flip-flop,

output gates coupling outputs of respective preselection flip-flops to said separate output leads,

a first oscillation-controlled means coupled. to shift gates and output gates associated with said cascaded preselection flip-flops to provide sequential output clock pulses from said cascaded preselection flip-flop,

a second oscillation-controlled means coupled to the output gate associated .with said last preselection flipfiop, and

at least one transfer gate means responsive to a control input signal, to the gated output of an'associated cascaded preselection flip-flop and to said first oscillation-controlled means to stop the output of said first oscillation-controlled means and cause an output from said second oscillation-controlled means, whereby to determine the number of sequential output clock pulses from said cascaded preselection flipfiops which precede an output clock pulse from said last preselection flip-flop.

9. A generator of a controllable number of sequential clock pulses for operating a computer, comprising a plurality of cascaded circuits and a last circuit, each of said circuits having an output lead for a respective out-put clock pulse,

a first alternator means having one output coupled to even ones of said cascaded circuits and having another output coupled to odd ones of said cascaded circuits to cause successive clock pulse outputs from said cascaded circuits,

a second alternator means interlocked with said first alternator means and having one output coupled to even ones of said cascaded circuits and having 'another output coupled to said last circuit, and

transfer gates each having an input coupled to the output lead of an associated cascaded circuit,

means to apply a pulse number control sign-a1 to enable any desired one of said transfer gates, the outputs of said transfer gates being coupled to at least one of said first and second alternator means to stop the first alternator means and activate the second alternator means, whereby the pulse member control signal determines the number of output clock pulses which precede the last output clock pulse.

ammo

10. A generator of a controllable number of sequential clock pulsesfor operating-a computer, comprising I a pluraliti .of cascaded p-reselectionflipflop circuits and a last preselection fiip-fiop circuit; each of said cirfor a respective output clock pulse, 7 a first alternator means having one output coupled to cuits having an out-put gate coupled toan output lead i even onesof said cascaded circuits and'having an-i even ones ofsaid cascaded circuits'and having an- 7 other output coupled to said last circuit and transfer gates each having an input coupled tot he output lead of an associated cascaded circuit, a

' meansto apply a pulse number control signal to enable any desired one of said transfer gates, the outputs of 7 said transfer gates being coupled to; at least one of said first and second alternator means to stop the first alternator means and activate the secondalternator means, whereby the pulse number control signal determines the number of output clock pulses'which precede the last output clock pulse, 7 No references cited. 

1. MEANS FOR GENERATING A CONTROLLABLE NUMBER OF SEQUENTIAL CLOCK PULSES, COMPRISING A PLURALITY OF CASCADED CIRCUITS AND A LAST CIRCUIT, EACH OF SAID CIRCUITS HAVING AN OUTPUT LEAD, A FIRST OSCILLATION-CONTROLLED MEANS COUPLED TO SAID CASCADED CIRCUITS TO CAUSE SUCCESSIVE CLOCK PULSE OUTPUTS FROM SAID CASCADED CIRCUITS, A SECOND OSCILLATION-CONTROLLED MEANS COUPLED TO SAID LAST CIRCUIT, AND TRANSFER GATE MEANS RESPONSIVE TO OUTPUTS OF SAID CASCADED CIRCUITS AND TO A PULSE NUMBER DETERMINING INPUT SIGNAL TO STOP SAID FIRST OSCILLATION-CONTROLLED MEANS AND ACTIVATE SAID SECOND OSCILLATION-CONTROLLED MEANS. 